1. Technical Field
Various embodiments of the present invention relate to a semiconductor memory apparatus and related methods. In particular, certain embodiments relate to a technology of performing a data is erasing operation.
2. Related Art
A flash memory apparatus, which is a representative example of a non-volatile memory apparatus, includes a non-volatile memory cell array. Each non-volatile memory cell includes a transistor having a control gate and a floating gate.
Among a memory cell, a single-level cell (SLC) capable of storing 1-bit data has two threshold voltage distributions. A multi-level cell (MLC) capable of storing 2-bit data has four threshold voltage distributions. A threshold voltage distribution at the lowest level is formed when an erase operation is performed. Here, the threshold voltage distribution may be called a data distribution, which is similar to a Gaussian distribution.
If the level of the threshold voltage distribution formed when the erase operation is performed is substantially lower than that of an erase verification voltage, a programming operation is performed once again after the erase operation to form a threshold voltage distribution with a desired voltage level and shape. The programming operation performed after the erase operation for that purpose is defined as a soft programming.
Furthermore, if the level of the threshold voltage distribution formed when the erase operation is performed is higher than the erase verification voltage, it may be necessary to perform the erase operation once again by increasing the voltage level of an erase voltage pulse.